Wafer chuck, exposure system, and method of manufacturing semiconductor device

ABSTRACT

In a wafer chuck for flatly vacuum-chucking a semiconductor wafer ( 11 ) supported by support pins ( 15 ) such that a pressure in a suction chamber ( 13 ) surrounded by an external wall ( 12 ), the upper surface of the external wall ( 12 ) is formed to be lower than the upper surfaces of the support pins, and the upper surface of the external wall ( 12 ) does not pressure the semiconductor wafer ( 11 ), a distance (L 1 ) between the external wall ( 12 ) and closest support pins ( 15   a ) is up to 1.8 mm, and an alignment pitch. (L 2 ) of the support pins ( 15 ) aligned inside the closest support pins ( 15   a ) to the external wall ( 12 ) is not more than 1.5 times of the distance (L 1 ) between the external wall ( 12 ) and the closest support pins ( 15   a ).

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority from and incorporates by reference thesubject matter of PCT Application No. PCT/JP01/0053 filed on Jan. 26,2001 and Japanese Patent Application No. 2000-20036 filed on Jan. 28,2000.

TECHNICAL FIELD

The present invention relates to a wafer chuck and an exposure techniquewhich use the wafer chuck, and to a manufacturing technique ofsemiconductor device and, more particularly, to a technique which iseffectively applied to a wafer chuck or the like used forvacuum-chucking a semiconductor wafer in the steps in manufacturing asemiconductor device.

BACKGROUND ART

For example, in an exposure system which coats a resist on asemiconductor wafer and which exposes and develops a circuit pattern ofone layer formed on a reticle serving as an original so as to form apredetermined resist pattern on the semiconductor wafer, the degree offlatness of the semiconductor wafer is an important technical object inorder to prevent resolving defects caused by not obtaining an imageformation within a focal depth and to form a sharp circuit pattern. Forthis reason, a flat state of the semiconductor wafer is to be requiredby such a way that the wafer is vacuum-chucked from the rear surfacethereof by a wafer chuck having a high degree of flatness. An exposureprocess is performed to the wafer.

As an example in which such an exposure system is described in detail,“VLSI MANUFACTURING AND TEST DEVICE GUIDEBOOK IN 1998” issued by KogyoChosakai Publishing Co., Ltd. (Nov. 20, 1997) is known. The wafer chuckhas a configuration in which a large number of support pins areimplanted inside a cap-like vessel. However, in this structure, theouter peripheral wall of the cup-like vessel and the large number ofsupport pins are brought into contact with the rear surface of thesemiconductor wafer so as to apply the negative pressure into thecap-like vessel, thereby supporting the semiconductor wafer. Therefore,warpage of the peripheral portion of the semiconductor wafer is notsufficiently corrected. Since micropatterning in a process makes thefocal depth further small, flattening a semiconductor wafer in exposurebecomes an important technical object every year.

With respect to the art, as an important which increases the degree offlatness in the peripheral portion of a semiconductor wafer, an artdisclosed in Japanese Patent Application Laid-Open No. 8-37227 is known.This art can achieve a predetermined effect such an in correction ofupward warping transformation at the peripheral portion of thesemiconductor wafer.

SUMMARY OF THE INVENTION

However, in the wafer chuck described in the above conventional art, asufficient degree of flatness cannot be achieved. More specifically,when a wafer is warped reversely (downwardly) in the above invention,the invention does not disclose a predetermined relationship in shapewhich corrects the warpage so that wafer correction for realizing a highdegree of flatness in the entire area of the semiconductor wafer has agiven limit.

It is an object of the present invention to provide a technique whichcan more effectively prevent warpage of a semiconductor wafervacuum-chucked on a wafer check and which can realize a high degree offlatness of the entire area of the semiconductor wafer.

It is another object of the present invention to provide a techniquewhich can vacuum-chuck semiconductor wafers having various diameters onsingle wafer chuck.

It is still another object of the present invention to provide atechnique which can improve the manufacturing yield of semiconductordevices.

The above objects and other objects of the present invention and novelcharacteristic features will be apparent from the description of thisspecification and the accompanying drawings.

The outline of typical one of the aspects of the present invention willbe briefly described below.

More specifically, a wafer chuck according to the present invention isadopted to flatly vacuum-chucks a semiconductor wafer having a rearsurface which is held on support pins by suction with a suction chamberat a negative pressure applied thereto, the suction chamber surroundedby an external wall, wherein the upper surface of the external wall isformed to have a level slightly lower than those of the upper surfacesof the support pins; the external wall does not chuck the semiconductorwafer and does not in contact with the semiconductor wafer; and air isslightly sucked into the suction chamber.

In addition, the wafer chuck is characterized in that the distancebetween the external wall and the closest support pin is kept constant,a moment is generated such that the gradient of the semiconductor waferbeing in contact with the outermost closest support pin is small, andflexure of the semiconductor wafer caused by vacuum is minimum.

An exposure system according to the present invention is characterizedby being constituted by using the wafer chuck.

A method of manufacturing a semiconductor device according to thepresent invention applies the wafer chuck to the step of polishing asemiconductor wafer and an exposure system for exposing thesemiconductor wafer to manufacture a semiconductor device.

According to the wafer chuck having the above constitution, inflow airgenerates a pressure loss by the external wall to make the pressure inthe suction chamber negative, a vacuum pressure between the externalwall and the closest support pin is generated by the negative pressure.When a moment generated by the vacuum pressure is equal to moment actingon the internal side of the closest support pin, the wafer is notinclined at a position above the closest support pin because the momentsare balanced.

In addition, when the distance between the external wall and the closestsupport pin is not more than a predetermined distance, flexure orgradient of the wafer from the closest support pin to an external bankcan be made sufficiently small. For this reason, the degree of flatnessof the wafer near the peripheral portion of the wafer can be maintainedat high accuracy.

According to the exposure system using the wafer chuck described above,even in a micropatterning process having a small focal depth, apreferable circuit pattern can be transferred to a semiconductor wafer.

According to the method of manufacturing a semiconductor using the waferchuck or the exposure system, a semiconductor device can be manufacturedeven in a micropatterning process having a small focal depth.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual diagram showing an exposure system using a waferchuck according to an embodiment of the present invention.

FIG. 2 is a perspective view showing the wafer chuck according to theembodiment of the present invention and a semiconductor wafer.

FIG. 3 is a plan view of the wafer chuck according the embodiment of thepresent invention.

FIG. 4 is a schematic sectional view of a part along a line A—A in FIG.3.

FIG. 5 is a sectional view showing a modification of the wafer chuckaccording to the embodiment of the present invention.

FIG. 6 is a plan view showing a modification of the wafer chuckaccording to the embodiment of the present invention.

FIG. 7 is a flow chart showing an example of a method of manufacturing asemiconductor device according to the embodiment of the presentinvention.

FIG. 8 is a diagram for explaining an example of the operation of thewafer chuck according to the embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described below in detailwith reference to the drawings.

(Embodiment 1)

FIG. 1 is a schematic diagram showing an exposure system using a waferchuck according to an embodiment of the present invention, FIG. 2 is aperspective view showing the wafer chuck and a semiconductor wafer, FIG.3 is a plan view of the wafer chuck in FIG. 2, and FIG. 4 is a schematicsectional view of a part along a line A—A in FIG. 3.

As shown in FIG. 1, an exposure system provided with a wafer chuck uses,for example, an Hg lamp 2 as an exposure light source. Exposure light 3emitted from the Hg lamp 2 is converged by an elliptic mirror 4 and thenconverged by a condensing lens 8 through a reflector 5, a relay lens 6,and a reflector 7. The light passing through the illumination systemtakes a circuit pattern formed in a reticle 9, and is reduced by areduction lens 10, so that the light is finally projected on asemiconductor wafer 11 chucked by a wafer chuck 1. In this manner, thecircuit pattern is transferred onto the semiconductor wafer 11 on whicha resist is coated.

The wafer chuck 1 is comprised of a material such as ceramics to preventtransformation caused by aging or thermal expansion and is arranged tochuck the semiconductor wafer 11. As shown in FIG. 2, the wafer chuckincludes a suction chamber 13 which is surrounded by an external wall 12and which is formed in a chuck body 14. The suction chamber 13 isconnected to an external exhaust pump or the like (not shown) through asuction hole 16. As shown in FIG. 3, the external wall 12 is formed tohave a size which is slightly smaller than that of the semiconductorwafer 11, and is curved to the rear surface of the semiconductor wafer11 to prevent adhesion or the like of the coated resist solution.

The upper surface of the external wall 12 is designed to be slightlylower than the level of a plurality of support pins 15 which support thesemiconductor wafer 11 from its rear surface. The rear surface of thesemiconductor wafer 11 and the upper surface of the external wall 12have a small gap δ. Therefore, the suction chamber 13 from which air isexhausted through the suction hole 16 communicates with the outsidethrough the gap. A leakage flow rate Q is expressed by the followingequation from theoretical calculation and an experimental result.

Q=3bδ ³/4μ·dp/dx  (Equation 1)

where, b: peripheral length of external wall, δ: gap, μ: viscositycoefficient, dP/dx: pressure gradient. As shown in Equation 1, when thegap is made small, the viscosity of air flowing in the gap stronglyacts, and a pressure loss generated when air passes through the externalwall 12 (vacuum seal is established from when the pressure loss isgenerated).

As an experimental example, the semiconductor wafer 11 (rear surface issatin-finished) having a diameter φ of 200 was used, the width of theexternal wall 12 was 0.3 mm, the gap δ was 0.5 μm, and the pressure of avacuum source was 0.79 kPa (600 mmHg). In this case, a decrease inpressure caused by inflow of air from the external wall 12 was 3.2%. Inthe same way, a decrease in pressure in a conventional structure inwhich the external wall 12 was in contact with a pin was 1.3%. When thewidth of the external wall 12 and the gap δ are changed, a decrease inpressure can be controlled. For this reason, the wafer chuck 1 whichcopes with a change in diameter of the semiconductor wafer 11 tan bemanufactured.

When the semiconductor wafer 11 are supported by the sharp-pointedsupport pins 15, the pressing pressures are generated at the tops of thesupport pins 15 due to a pressure difference dP between the pressure ofthe suction chamber 13 and the atmospheric pressure. However, it isexperientially known that a result is obtained on the assumption thattransformation of a portion pressed by a continuous surface such as thesurface of the external wall 12 is different from transformation of aportion pressed by the tops of the support pins 15. This difference isrelated to a vacuum pressure, the areas of the tops of the pins, thearrangement of pins, the condition of the rear surface of thesemiconductor wafer 11, and the like.

In this embodiment, although no continuous contact portion is providedbetween the rear surface of the semiconductor wafer 11 and the uppersurface of the external wall 12, the arrangement of the support pins 15must be considered. When the alignment pitches of the support pins 15are set as equal as possible, and when closest support pins 15 a to theexternal wall 12 is arranged to receive vacuum pressures which are equalto each other, the highest degree of flatness can be obtained regardlessof the condition of the rear surface of the semiconductor wafer 11. Morespecifically, the support pins 15 a may be arranged such that a distance(distance L1) between the external wall 12 and the closest support pin15 a is almost equal to half an alignment pitch L2 of the support pins15. When an accuracy error of within ±50 nm is set on a target, thealignment pitch L2 of the internal support pins 15 and the distance L1between the external wall 12 and the closest support pin 15 a desirablysatisfy a relation: L2/6≦L1≦L2.

The relation between the distance L1 between the external wall 12 andthe closest support pins 15 a and the alignment pitch L2 of the internalsupport pins 15 can be applied to not only alignment pitches in a radialdirection of the wafer chuck as described above but also alignmentpitches in a circumferential direction.

More specifically, from a viewpoint that the pressures received by thesupport pins are set as equal as possible, the alignment pitch L2 is setto be not more than 1.5 times the distance L1 between the external wall12 and the closest support pins 15 a for the following reason.

It must be necessary for realizing a high degree of flatness of thesemiconductor wafer 11 that pressures acting on the tops of the supportpins 15 are set as equal as possible. That is, in vacuum chucking, anarea on which the atmospheric pressure acts is equally shared by thesupport pins 15.

In particular, a problem is outstandingly posed at a peripheral portion(internal wall 17) of a press-up hole 18 into/from which a press-up pin19 for pressing the semiconductor wafer 11 illustrated in FIG. 5 (to bedescribed later) enters. Especially, pressures acting on the tops of theclosest support pins 15 a to the internal wall 17 is considerablyinfluenced on the degree of flatness.

An experimental check for forecasting distortion is performed withrespect to this influence.

In the experiment, as illustrated in FIG. 8, the ratio of the density ofalignment of the closest support pins 15 a which were closest to theinternal wall 17 to the density of alignment of support pins 15 b whichwere adjacently outside the alignment of the closest support pins 15 awas changed to 1.5 times, and the ratio of a pressure P1 (pressure ofarea {circle around (1)}) acting on the top of the support pin 15 a to apressure P2 (pressure of area {circle around (2)}) acting on the top ofthe support pin 15 b was set to be 1.5 times to 1/1.5 times. In thiscase, a distortion of about 90 nm was measured. Since the distortion is100 nm or less because of other factors, it is considered that the ratioof 1.5 times is the limit of practical use. As a matter of course, inorder to obtain a higher accuracy, the ratio should be made closer aspossible to 1.0 times rather than 1.5 times.

The value L2 must be 1 mm or more because of restrictions or the like ofactual processing technology of the wafer chuck 1. On the assumption, ifP1/P2={circle around (1)}/{circle around (2)} is allowed to be 1.5 timesto 1/1.5 times as described above, the minimum value the value L2 is 1mm as described above, in order to control the ratio of area {circlearound (1)} to area {circle around (2)} to 1.5 times to 1/1.5 times, thefollowing conditions are satisfied.

When the ratio is 1.5 times, L1=L2 is satisfied because L2/2+L1(=L2)=1.5 times L2 is satisfied.

When the ratio is 1/1.5 times, L1=1/6=0.17 mm because L2/2+L1(=L2/6)=L2·2/3 is satisfied.

However, since L1 is limited to about 0.2 mm due to the restrictions ofprocessing technology, the minimum value of L1 is 0.2 mm.

On the other hand, the distance L1 between the external wall 12 and theclosest support pin 15 a is desirably set to be up to about 1.8 mm inconsideration of flexure of a beam.

The reason why the distance L1 between the external wall 12 and theclosest support pins 15 a is set to be up to 1.8 mm will be describedbelow.

It is assumed that pitches of the closest support pins 15 a to theexternal wall 12 and the support pins 15 b which are internally adjacentto the closest support pins 15 a are represented by L2, an overhang(i.e., distance between the external wall 12 and the closest support pin15 a) of the peripheral portion of the semiconductor wafer 11 isrepresented longitudinal by L1, a distributed load is represented by w,a longitudinal elastic coefficient E, and a geometrical moment ofinertia is represented I. In this case, a flexure y of the distal end(immediately above the external wall 12) of the overhang isapproximately expressed by the following equation:

y=w(L 1)⁴/8EI+w(L 1)³ L 2/6E 1  (Equation 2)

An Si substrate is supposed as the semiconductor wafer 11, 80 kPa (600mmHg) are substituted to w, 1.8 mm are substituted to L1, 2 mm aresubstituted to L2, 166 MPa is substituted to E, and the thickness of thesemiconductor wafer 11 is given by 0.725 mm→I=0.0318 mm⁴. In this case,the flexure y is given by y=50 nm. In order to achieve a degree offlatness of 100 nm or less, it is proper that the factor of flexure isset to be 50 nm or less. For this reason, it is considered as thenecessary condition that L1 is 1.8 mm or less.

(Embodiment 2)

In the wafer chuck 1 according to Embodiment 1, an inflow rate ofexternal air changes depending on the distance of the gap between thesemiconductor wafer 11 and the upper surface of the external wall 12.The inflow rate of the air is expressed by Equation 1. In this case,when the gap δ is excessively large, the inflow rate of the gasincreases to decrease the pressure in the suction chamber 13. When theinflow rate is excessively small, the semiconductor wafer 11 is broughtinto contact with the upper surface of the external wall 12, and theeffect described in Embodiment 1 may not be achieved. In addition, whenforeign material adhered to the rear surface of the semiconductor wafer11 is sandwiched between the semiconductor wafer 11 and the externalwall 12, the foreign material mounds the corresponding portion of thesemiconductor wafer 11 and may deteriorate the degree of flatness.

In an experiment, it is assumed that a semiconductor wafer 11 having adiameter φ of 200 and a satin-finished rear surface is used, the widthof the external wall 12 is 0.3 mm, and the gap distance is 0.5 μm. About3% of pressure in the suction chamber 13 decreases. It is assumed thatan actual tolerance of a decrease in pressure is set to be 10%. Thevalue is applied to Equation 1.

When the width of an external wall is 0.3 mm, the gap δ is 0.75 μm atthe maximum; and when the width of the external wall is 2.0 mm, the gapδ is 1.4 μm at the maximum, so that such values are considered to themaximum until which the gap δ can be set.

In addition, a gap δ of 0.1 μm or more is required at the minimum suchthat the semiconductor wafer 11 is not brought into contact with theexternal wall 12.

When the width of the external wall 12 is 2.0 mm or more, the flexure ofthe peripheral portion of the semiconductor wafer 11 increases due tothe influence of a vacuum pressure. For this reason, it is desirablethat the width is set to be 2.0 mm or less.

(Embodiment 3)

In the wafer chuck 1 according to Embodiment 1 wherein the closestsupport pins 15 a are arranged to be in one circle along the externalwall 12 and the support pins 15 b on the second circular line arearranged inside the closest support pins 15 a to be in one circle, theinterval between the closest support pins 15 a and the support pins 15 bis important to obtain the high accuracy of the degree of flatness ofthe peripheral portion of the semiconductor wafer 11.

More specifically, in a semiconductor wafer 11 warped at an averagecurvature of 1/R, the semiconductor wafer 11 should be vacuumed so as tocorrect the warpage, so that an arrangement condition of the supportpins 15 for performing correction at the outermost portion is required.

In the structure of a wafer chuck of a conventional art, the externalwall 12 is in contact with the semiconductor wafer 11 to serve as avacuum seal. For this reason, at the portion where the semiconductorwafer 11 is in contact with the external wall 12, the average curvatureof the semiconductor wafer 11 cannot be sufficiently corrected to leavea gradient.

In this embodiment, the gradient of the semiconductor wafer 11 can bedecreased at the contact portions to the semiconductor wafer 11 of theclosest support pins 15 a to the external wall 12, and the support pins15 b on the second circular line are arranged inside the outermost pins15 a to form in one circle such that contact surface pressures of theclosest support pins 15 a to the external wall 12 are equal to those ofthe other support pins 15, so that the arrangement density of thesupport pins 15 is made uniform and that the degree of flatness of aportion near the external wall 12 where a high degree of flatness cannotbe easily obtained, can be improved. In this case, as described above,the distance (alignment pitch L2) between the closest support pins 15 ato the external wall 12 and the support pins 15 b on the second circularline is preferably set to be a value falling within a range of 1 to 2.5mm, more preferably, 2 mm in order to easily obtain the accuracy of thedegree of flatness of the semiconductor wafer 11

The case in which the areas of the tops of the support pins 15 are setequal to each other has been described above. However, in the case wherethe arrangement density of the support pins 15 is not uniform, the areasof the tops of the support pins 15 may be changed depending on thedensity.

(Embodiment 4)

In each of the wafer chucks 1 according to Embodiments 1 to 3, the sameoperational effects as those to the external wall 12, the closestsupport pins 15 a, and the support pins 15 b on the second circular linecan be obtained for an internal wall 17 having a press-up hole 18 for apress-up pin 19 arranged a portion near the center of the wafer chuck 1as shown in FIG. 5 and used to convey the semiconductor wafer 11, forthe closest support pins 15 a to the internal wall 17, and for thesupport pins 15 b on the second circular line from the internal wall.

As described above, the wafer chuck 1 described in this embodimentprevents warpage near the external wall 12 of the chucked semiconductorwafer 11 and the internal wall 17 to flatly chuck the semiconductorwafer 11. For this reason, when this embodiment is applied to the waferchuck 1 of an exposure system illustrated in FIG. 1, a circuit patternhaving a preferable resolution can be transferred to the semiconductorwafer 11 without changing focal lengths of the reduction lens 10 to therespective parts of the semiconductor wafer 11.

(Embodiment 5)

In the embodiment described above, the case in which the semiconductorwafer 11 having a specific size is vacuum-fixed by one external wall 12has been exemplified. However, external walls 12 having differentdiameters may be arranged at once, and a plurality of semiconductorwafers 11 having different sizes may be vacuum-fixed.

More specifically, in the wafer chuck 1 illustrated in FIG. 6, anexternal wall 12A is arranged inside the external wall 12. In thismanner, one wafer chuck 1 can be used to vacuum-fix any one of asemiconductor wafer 11 having a small diameter corresponding to theexternal wall 12 and of a semiconductor wafer 11 having a large diametercorresponding to the external wall 12A.

In this case, the external wall 12 and the external wall 12A are not incontact with the rear surface of the semiconductor wafer 11 even thoughany one of the wafers semiconductor wafers 11 having the small diameterand the large diameter. For this reason, when the configuration of theinternal wall 17, the press-up hole 18, the press-up pin 19, and thelike which are illustrated in FIG. 5 is merely arranged at the centralportion of the innermost external wall 12, negative-pressure vacuum onthe entire surface of the semiconductor wafer 11 can be realized.

According to Equation 1, a linkage Q is in proportion to a peripherallength b. For this reason, in order to maintain dP at a value requiredfor vacuum, a gap δ between given walls must be smaller than a gap δbetween walls outside the given walls.

When semiconductor wafers having different diameters are not targeted,and when a semiconductor wafer having a large warpage is vacuumed, thesemiconductor wafer is sequentially vacuumed from the central portion.In this manner, problems of vacuum fault caused by warpage can beconsiderably reduced. In this case, the difference between the levels ofinternal banks (peripheral walls) is set to be up to 0.3 mm which isgenerally considered as a limit for reliably performing vacuuming, andmay be set to be 0.1 μm or more.

(Embodiment 6)

FIG. 7 illustrates a flow chart showing an example of a method ofmanufacturing a semiconductor device using the wafer chuck and theexposure system including the wafer chuck.

More specifically, a semiconductor substrate obtained by slicing aningot consisting of monocrystalline semiconductor is polished tomanufacture a semiconductor wafer 11 (step 101).

In the known wafer process, a circuit pattern for a semiconductor deviceis transferred to and formed on the semiconductor wafer 11 byphotolithography using the exposure system in FIG. 1. At this time, whenthe wafer chuck 1 according to each of the embodiments described aboveis used to fix the semiconductor wafer 11 to the exposure system, thecircuit pattern having a preferable resolution can be transferred to thesemiconductor wafer 11 without changing the focal lengths of thereduction lens 10 to the respective parts of the semiconductor wafer 11.

In this wafer process, the surface of the semiconductor wafer 11 isflattened by a CMP (chemical mechanical polishing) technique or the liketo prevent adverse affect to an uneven upper surface of the wafer baseportion in a multilevel interconnection structure or the like. When thewafer chuck 1 according to each of the embodiments is used to chuck thesemiconductor wafer 11 in a polishing device for executing the CMPtechnique, high-level flattening can be performed such that maximumflexures at the respective parts of the semiconductor wafer 11 arecontrolled to 50 nm or less, reduction or the like of circuit patterndefects of the upper layer caused by the unevenness or the like of thebase can be realized (step 102).

In the semiconductor wafer 11 on which a large number of semiconductordevices are formed at once by the above wafer process, the functions ofthe respective semiconductor devices are inspected by a wafer probe orthe like (step 103). Furthermore, in the dicing step for thesemiconductor wafer 11, the plurality of semiconductor devices areseparated into independent chips (pellets) (step 104), and only chipswhich are determined as nondefective chips in the inspection step instep 103 are packaged (step 105).

In this manner, semiconductor devices serving as products are completed.In this embodiment, as described above, the semiconductor wafer 11 ischucked by the wafer chuck 1 with a high degree of flatness and exposed.For this reason, high accuracy of focal lengths of the reduction lens 10to the respective parts of the semiconductor wafer 11 is achieved, andimprovement in transfer accuracy of a circuit pattern can be realized.

When the wafer chuck 1 according to this embodiment is applied to theCMP step, reduction of defects such as disconnection in a multi-layeredinterconnection structure can be realized by high-level flattening ofthe semiconductor wafer 11 in the CMP step. As a result, a high yield inthe steps in manufacturing semiconductor devices can be achieved.

The present made by the present inventor has been concretely describedon the basis of the embodiments. However, the present invention is notlimited to the embodiments, and various changes and modifications can beeffected without departing from the spirit and scope of the invention asa matter of course.

In the above description, the invention made by the present inventionhas been explained with respect to an optical exposure system in thefield of the invention which is the background of the invention.However, the present invention is not limited to the optical exposuresystem, and the present invention can be applied to an electron beamexposure system, and not only these exposure systems, but also varioussemiconductor manufacturing devices and semiconductor inspection deviceswhich must flatly chuck semiconductor wafers.

In addition, the present invention can be applied to not only the stepsin manufacturing a semiconductor device but also the steps inmanufacturing liquid crystal or the like.

INDUSTRIAL APPLICABILITY

Effects obtained by typical one of the aspects of the inventiondisclosed in this application will be briefly described below.

More specifically, according to the wafer chuck of the presentinvention, when external air is sucked into a suction chamber by a spacebetween a semiconductor wafer and the upper surface of an external wall,a pressure loss caused by a viscosity resistance to establish a vacuumseal between the suction chamber and the outside, and the semiconductorwafer can be vacuum-chucked by only support pins. In this manner,uniform vacuum chucking can be performed in an entire area subject towafer vacuuming, and vacuum chucking can be performed with an extremelyhigh degree of flatness.

According to the wafer chuck of the present invention, an effect thatsemiconductor wafers having various diameters can be vacuum-chucked byone wafer chuck can be achieved.

According to an exposure system using the wafer according to the presentinvention, since the degree of flatness of a chucked semiconductor waferincluding its peripheral portion increases, focal lengths do not changein the entire area of the semiconductor wafer, and a circuit patternhaving a preferable resolution can be transferred to the semiconductorwafer.

When a wafer chuck according to the present invention is used in asemiconductor wafer polishing device, a polished surface having a highdegree of flatness can be obtained.

According to the above (3) and (4), in a method of manufacturing asemiconductor device using the wafer chuck of the present invention,non-defective semiconductor chips can be manufactured in the entire areaof the semiconductor wafer, and an yield of semiconductor devices can beincreased.

What is claimed is:
 1. A wafer chuck for flatly vacuum-chucking asemiconductor wafer supported on support pins by suction with a suctionchamber at a negative pressure applied thereto, said suction chambersurrounded by a first peripheral wall, wherein: an upper surface of thefirst peripheral wall is formed to be lower than upper surfaces of thesupport pins, and the upper surface of the first peripheral wall is notin contact with the semiconductor wafer; and a first distance betweenthe first peripheral wall and first closest support pins of the supportpins is set to be shorter than a second distance between the firstsupport pins and second support pins positioned inside the first supportpins.
 2. A wafer chuck according to claim 1, wherein the first distanceis not less than 0.2 mm and not more than 1.8 mm.
 3. A wafer chuckaccording to claim 1, wherein a difference between the level of theupper surface of the first peripheral wall and the level of the uppersurfaces of the support pins falls within a range of 0.1 μm to 1.4 μm.4. A wafer chuck according to claim 1, wherein the first support pinsare arranged to make one circle along the first peripheral wall, and thesecond support pins on a second circular line are arranged inside theclosest support pins with a distance falling within a range of 1 mm to2.5 mm.
 5. A wafer chuck according to claim 1, wherein at least onesecond peripheral wall is arranged inside the first peripheral wall, apositional relationship between the first support pins and the secondperipheral wall inside or outside the second peripheral wall isequivalent to a positional relationship between the first peripheralwall and the first support pins in the wafer chuck.
 6. A wafer chuckaccording to claim 5, wherein a difference between the level of theupper surface of the second peripheral wall and the level of the uppersurface of the first support pins falls within a range of 0.1 μm to 0.3mm.
 7. A wafer chuck according to claim 5, wherein the support pins arenot arranged inside the second peripheral wall, and a pressure insidethe second peripheral wall is the atmospheric pressure.
 8. An exposuresystem including a wafer chuck on which a semiconductor wafer is placed;exposure light source; and a projection optical system for irradiatingexposure light emitted from the exposure light source, passing throughan exposure original on the semiconductor wafer, wherein the wafer chucksupports the semiconductor wafer on support pins by suction with asuction chamber at a negative pressure applied thereto, said suctionchamber surrounded by a first peripheral wall, wherein: an upper surfaceof the first peripheral wall is formed to be lower than upper surfacesof the support pins, and the upper surface of the first peripheral wallis not in contact with the semiconductor wafer; and a first distancebetween the first peripheral wall and first closest support pins of thesupport pins is set to be shorter than a second distance between thefirst support pins and second support pins positioned inside the firstsupport pins.
 9. A method of manufacturing a semiconductor device whichperforms wafer processes including a polishing process and aphotolithography process to a semiconductor wafer to form asemiconductor device, wherein a wafer chuck for chucking thesemiconductor wafer is used in at least one of the polishing process andan exposure system used in the photolithography process, wherein thewafer chuck supports the semiconductor wafer on support pins by suctionwith a suction chamber at a negative pressure applied thereto, saidsuction chamber surrounded by a first peripheral wall, wherein: an uppersurface of the first peripheral wall is formed to be lower than uppersurfaces of the support pins, and the upper surface of the firstperipheral wall is not in contact with the semiconductor wafer; and afirst distance between the first peripheral wall and first closestsupport pins of the support pins is set to be shorter than a seconddistance between the first support pins and second support pinspositioned inside the first support pins.
 10. A method of manufacturinga semiconductor device according to claim 9, characterized in that thepolishing process is a chemical mechanical polishing (CMP) process.